CPU Course Review - 05. Accumulator (0 ~ 9)

1. Title

0 ~ 9 까지 누산 하는 시스템 설계

2. Category

"System Verilog", "BASYS3", "VIVADO"

 

3. Key Concepts

Convert C Code to SystemVerilog

 

4. Setup

 

C 코드로 구현된 0~9까지 누산하는 프로그램을 SystemVerilog로 구현한다.

 

5. Code Review

module Dedicated_Processor_Accumulator(
        input logic clk, reset,
        output [7:0] outbuf
    );

    logic AsrcMUXsel, BsrcMUXsel, ALoad, BLoad, Alt10;

    control_unit U_CONTROLLER(
        .*
    );

    data_path U_DATA_PATH(
        .*
    );

endmodule

 

 

module control_unit (
    input  logic  clk, reset,
    input  logic  Alt10,
    output logic  AsrcMUXsel, BsrcMUXsel, ALoad, BLoad
);

    typedef enum bit [2:0] {S0, S1, S2, S3} state_e;
    state_e state, next_state;

    always_ff @( posedge clk, posedge reset ) begin
        if(reset) begin
            state <= S0;
        end else begin
            state <= next_state;
        end
    end

    always_comb begin

        next_state = state;
        AsrcMUXsel = 0;
        BsrcMUXsel = 0;
        ALoad = 0;
        BLoad = 0;

        case (state)
            S0: begin
                AsrcMUXsel = 0;
                BsrcMUXsel = 0;
                ALoad = 1;
                BLoad = 1;
                next_state = S1;
            end
            
            S1: begin
                AsrcMUXsel = 0;
                BsrcMUXsel = 0;
                ALoad = 0;
                BLoad = 0;

                if(Alt10) begin
                    next_state = S2;
                end else begin
                    next_state = S3;
                end
            end
            
            S2: begin
                AsrcMUXsel = 1;
                BsrcMUXsel = 1;
                ALoad = 1;
                BLoad = 1;
                next_state = S1;
            end
            
            S3: begin
                AsrcMUXsel = 0;
                BsrcMUXsel = 0;
                ALoad = 0;
                BLoad = 0;
                next_state = S3;
            end
        endcase
        
    end

endmodule

module data_path (
    input   logic clk, reset,
    input   logic AsrcMUXsel, BsrcMUXsel, ALoad, BLoad,
    output  logic Alt10,
    output  logic [7:0] outbuf
);

    logic [7:0] A_adder_result, B_adder_result, AsrcMUXout, BsrcMUXout, Aregout, Bregout;

    mux_2x1 U_A_MUX_2X1(
        .sel(AsrcMUXsel),
        .x0(8'b0), .x1(A_adder_result),
        .y(AsrcMUXout)
    );
    
    mux_2x1 U_B_MUX_2X1(
        .sel(BsrcMUXsel),
        .x0(8'b0), .x1(B_adder_result),
        .y(BsrcMUXout)
    );

    register U_A_REGISTER(
        .clk(clk), .reset(reset),
        .load(ALoad),
        .d(AsrcMUXout),
        .q(Aregout)
    );
   
    register U_B_REGISTER(
        .clk(clk), .reset(reset),
        .load(BLoad),
        .d(BsrcMUXout),
        .q(Bregout)
    );

    adder U_A_ADDER(
        .a(Aregout),
        .b(8'h01),
        .sum(A_adder_result)
    );

    adder U_B_ADDER(
        .a(Bregout),
        .b(Aregout),
        .sum(B_adder_result)
    );

    comparator U_COMPERATOR(
        .a(Aregout),
        .b(8'd10),
        .lt(Alt10)
    );
    
    register U_OUT_REGISTER(
        .clk(clk), .reset(reset),
        .load(clk),
        .d(Bregout),
        .q(outbuf)
    );

endmodule

 

6. Testing and Debugging

* Testing Tools: VIVADO, Modelsim

module tb_Dedicated_Processor(

    );

        logic clk, reset;
        logic [7:0] outbuf;

    Dedicated_Processor_Accumulator DUT(
        .*
    );

    always 
        #5 clk = ~clk;

    initial begin
        clk = 0;
        reset = 1;

        #20 reset = 0;

    end


endmodule