Verilog Course Review - 01. Adder

1. Title

Basic Gate & Adder using GPIO

2. Category

"Verilog", "BASYS3", "VIVADO"

 

3. Key Concepts

Instantiation

 

4. Setup

Code 구성

1) Design Sources : 실제 하드웨어 동작을 정의하는 코드 
2) Constraints : 설계가 실제 FPGA 하드웨어에서 올바르게 동작하도록 하기 위해 설정된 제약 조건 파일 
3) Simulation Sources : 설계된 회로의 동작을 시뮬레이션하고 검증하기 위한 테스트벤치와 입력 데이터

Half Adder Truth Table

Full Adder Truth Table

 

5. Code Review

 

module full_adder_4bit(
    input [3:0]a, b,
    input cin,
    output [3:0]sum,
    output carry
);

wire carry_w_01, carry_w_02, carry_w_03;

full_adder fa_0(
    .a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .carry(carry_w_01) 

);

full_adder fa_1(
    .a(a[1]), .b(b[1]), .cin(carry_w_01), .sum(sum[1]), .carry(carry_w_02)
);

full_adder fa_2(
    .a(a[2]), .b(b[2]), .cin(carry_w_02), .sum(sum[2]), .carry(carry_w_03)

);

full_adder fa_3(
    .a(a[3]), .b(b[3]), .cin(carry_w_03), .sum(sum[3]), .carry(carry)
);


endmodule


module full_adder(
    input a,b,cin,
    output sum, carry
    );

    wire w_sum, w_carry_01, w_carry_02;
    assign carry = w_carry_01 | w_carry_02;

    half_adder U_HALF_ADDER_01(
    .a(a), .b(b), .sum(w_sum), .carry(w_carry_01)
    );
    
    half_adder U_HALF_ADDER_02(
    .a(w_sum), .b(cin), .sum(sum), .carry(w_carry_02)
    );


endmodule


module half_adder(
   input a,b,
   output sum, carry 

);

    assign sum = a ^ b;
    assign carry = a & b;

endmodule

This Verilog code implements a 4-bit full adder using multiple 1-bit full adders.
The full_adder module is instantiated four times, each handling one bit of the input operands (a and b), and the carry is passed through between stages.
The half_adder module is used within the full_adder to compute the sum and carry for individual bits.

 

6. Testing and Debugging

* Testing Tools: VIVADO, Modelsim

module tb_adder(

    );

reg [3:0]a, b;
reg cin;
wire [3:0]sum;
wire carry;


full_adder_4bit DUT(
   .a(a), .b(b), .cin(cin),
   .sum(sum), .carry(carry) 
);


 integer i, j, k; // Loop variables

    initial begin
        // Iterate through all combinations of a, b, and cin
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                for (k = 0; k < 2; k = k + 1) begin
                    #10 a = i; b = j; cin = k; // Assign test values
                end
            end
        end
        #10 $finish; // End simulation
    end

endmodule